VLSI Device Simulation

Efficient VLSI Fault Simulation

Bipolar Device Modeling for VLSI Layout Verification

Today, layout verification for VLSI is a crucial part of IC design. However, for applicability, this must be both fast and accurate. Layout-to-circuit extractors can meet both these constraints. They quickly convert a layout into an equivalent network that accurately models that layout. Subsequently, circuit simulation and network comparison are convenient tools that enable accurate prediction ...

An Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation

A new parallel semiconductor device simulation using the dynamic load balancing approach is presented. This semiconductor device simulation based on adaptive finite volume, error estimation, and monotone iterative methods has been developed and implemented on a Linux-cluster with MPI library. Two different parallel versions of the algorithm to perform a complete device simulation are proposed. ...

Simulation of the Admittance Control Based Haptic Interface Device

Device structures and device simulation techniques